With development of computer architecture technologies, integration of a multi-core (Multi-Core) architecture or even a many-core (Many Core) architecture on a processor chip gradually becomes a mainstream. A chip of this architecture type is referred to as a multi-core processor chip, or referred to as a chip multi-processor (Chip Multi-Processors, CMPs) chip. An existing multi-core processor chip generally has a non-uniform cache architecture (Non-Uniformed Cache Architecture, NUCA). Specifically, each processor core (Core) privately owns a level 1 cache (Level 1 cache), and processor cores on a multi-core processor chip logically share a level 2 cache (Level 2 cache). However, because a cache capacity on a processor chip is limited, a part of data involved in a running process of a multi-core processor chip may also be stored in a memory device outside the multi-core processor chip. The multi-core processor chip communicates and the memory device performs communication by using a memory controller integrated on the multi-core processor chip.
A modern operating system provides an abstraction technology for memory management, namely, a virtual memory (Virtual Memory) technology. That is, programs run in virtual address space (Virtual Address Space), and any program uses an address in a virtual memory. The operating system assists a memory management unit (Memory Management Unit, MMU) in “conversion” of a virtual address sent by the program into a real physical address. A conversion relationship between a virtual address and a physical address is generally stored in a page table (Page Table). A page table occupies relatively large space and is therefore generally stored in a memory device outside a chip, and only some most frequently-used page tables are stored in a translation look-aside buffer (Translation Look-aside Buffer, TLB) on a processor chip.
Therefore, after obtaining a virtual address each time, a processor first queries, from a TLB, a physical address corresponding to the virtual address. If the physical address corresponding to the virtual address cannot be found in the TLB, the processor needs to query, from a memory device outside a chip, the physical address corresponding to the virtual address. Because a page table is generally designed with multiple levels, the processor needs to access the memory device multiple times to obtain the physical address needed by the processor. Consequently, each time of access to the memory device causes a burden to a communication channel on the processor chip.